In a network (M) which may be characterized by the quotient of a cross-quantity and a through-quantity, M=cross-quantity/through-quantity, it is generally known that certain relationships govern series and parallel network elements. For example, in an electrical resistor network, resistance (R) is the quotient of voltage (V) and current (i), R=V/i. It is well known that series elements are additive, e.g. Requivalent=(R1+R2+R3+ . . . RN), and that the equivalent resistance of parallel resistor elements is described by the relationship, Requivalent−1=(R1−1+R2−1+R3−1+ . . . RN−1). Such relationships hold true for other physical networks M as well.
In many engineering applications the problem of how to implement a network using multiple identical elements is encountered. Often such an implementation is sought in order to reduce the influence of unfavorable factors. In integrated circuit layout for example, the effects of an uneven temperature gradient, nonuniform distribution of process layers, and noise emissions from adjacent circuit blocks, may be alleviated by implementing a desired network value, such as resistance or capacitance, using smaller individual elements rather than using one lump-sum component.
Problems arise however, in attempting to describe a network using a combination of series and parallel elements. It is often desirable to use elements with matching physical characteristics. The use of matching network elements helps to equalize the effects of thermal gradients and material gradients and other unfavorable factors. The use of matching elements is also often desirable from a manufacturing standpoint. It is known in the arts to approach the breakdown of a network into series and parallel elements using some degree of trial and error. The problem is made more complex by concerns such as, in the example of integrated circuit and design, the desire to minimize area and the desire to minimize the count of individual network elements or to utilize elements of a particular value or size.
Techniques exist for systematically breaking down a network into series and parallel elements. See for example, the U.S. patent application Ser. No. 10/217,285 of Du and Jaska, filed Aug. 12, 2002, entitled “Implementation of Networks Using Parallel and Series Elements,” which is incorporated herein in its entirety for all purposed by this reference. However, once a network has been described in terms of subnetworks of series and parallel elements, the task of laying out the physical network remains a challenging one. In a resistor network for an integrated circuit for instance, a given element value is implemented using a resistor of the appropriate length and width. (Thickness is generally determined by the process and materials used). The network must then be implemented within area limitations. Typically a designer spends long hours attempting to determine a layout for the subnetworks of individual elements and interconnections. The task is complicated by the desirability of distributing elements of each subnetwork throughout the entire network to help alleviate the effects of unfavorable factors. Such cut-and-try layout techniques are tedious, time consuming, and error prone. Oftentimes network layouts have more than one hundred individual elements with the result that misplacement of elements detrimental to performance can go undetected. The number of possible permutations and lack of a systematic approach can lead to inconsistency from designer to designer, which can lead to further complications in circuits having numerous network blocks prepared by numerous designers.
It would be useful and advantageous in the arts to provide algorithms, systems, and methods for systematically laying out networks of parallel and series elements. Such tools could reduce tedium, error, time, cost, and inconsistency in preparing network layouts. Such tools could also be used to generate schematic diagrams describing networks in terms of series and parallel elements.